With ever-increasing memory footprints of current and future applications, larger caches provide substantial performance gains in each processor generation. Due to high power leakage and area, the size of static random access memory (SRAM)-based last level cache (LLC) may be limited. Recent non-volatile memory (NVM) technologies, like Spin Hall Effect (SHE) MRAM or Spin Transfer Torque Magnetic RAM (STTRAM), as examples, have emerged as promising alternatives for SRAM-LLC. These memories have significant capacity and power advantages as compared to SRAM, e.g., STTRAM is shown to have ten times lower power leakage and four times lower area consumption compared to SRAM. However, NVM-LLC may have higher write latency than write latency in SRAM-LLC. In NVM-LLC, read requests often wait in queues for high-latency write operations to finish, resulting in performance loss even with higher-capacity NVM-LLC.